Synchronous differential signaling protocol
US10305671B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 2016 |
| Grant date | May 28, 2019 |
| Priority date | — |
| Expiry date | Jun 28, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Synchronous, differential signaling may be performed over a communications path through a wired connection between a master device and a slave device to provide high-bandwidth and/or low-latency communications. Flexibility may be provided in the signaling protocol by providing for a configurable frame structure. Flexibility may be provided in mapping of data streams to bit slots in a frame, varying a number of downlink and uplink slots, configuring a number of turnarounds and locations of the turnarounds within a frame, configuring location and number of control word bit (CWB) slots in a frame, and/or adjusting a clock frequency of the communications link.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.