Patent · US Active

Using linked-lists to create feature rich finite-state machines in integrated circuits

US10310476B2 · kind B2 · utility

0Cited by

1References

20Claims

0Family size

Assignee

Analog Devices Global Unlimited Company · BM

Inventors

Navdeep Singh Dhanjal · San Jose, US
Shengbing Zhou · Beijing, CN

Key dates

Filing date	Apr 20, 2018
Grant date	Jun 4, 2019
Priority date	—
Expiry date	Apr 20, 2038

Classification

Technology area (CPC G)Physics
CPC primaryG05B2219/23289
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

An apparatus comprises an integrated circuit (IC) including sequencer circuitry; and a memory integral to or operatively coupled to the integrated circuit, wherein at least a portion of the memory is organized as a plurality of hierarchical linked lists defining a finite state machine of a plurality of finite IC states; wherein the sequencer circuitry is configured to: receive one or more control words from the hierarchical linked lists associated with an IC state; advance the IC to the IC state according to the one or more control words; and perform one or more actions corresponding to the IC state.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.