Memory control method and memory control apparatus
US10310772B2 · kind B2 · utility
Assignees
Inventor
Key dates
| Filing date | Nov 25, 2016 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Jan 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3431
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides memory control methods and memory control apparatus. An exemplary method includes providing a memory having a targeted memory zone, the targeted memory zone having a plurality of memory cells, and a storage capacity of each memory cell being one page; receiving and reading out to-be-stored data and obtaining the targeted address information of the to-be-stored data; reading out data status of all memory cells of a targeted memory zone; determining the data status of the memory cells of the targeted memory zone; performing a programming operation to a memory cell with an erased state to write the to-be-stored data into the memory cell with the erased state; and performing an erasing operation to a memory cell having a logic address of written data to remove the logic address.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.