Method and apparatus for processing memory page in memory
US10310971B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 17, 2017 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Jan 24, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2212/7208
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for processing a memory page in memory, where the memory page in the memory includes an idle single-level cell (SLC) memory page, an active SLC memory page, an inactive SLC memory page, and a multi-level cell (MLC) memory page, and when a quantity of idle SLC memory pages of any virtual machine (VM) is less than a specified threshold, the processing method includes converting one idle SLC memory page to two MLC memory pages, copying data in two inactive SLC memory pages to the two converted MLC memory pages, and releasing storage space of the two inactive SLC memory pages to obtain two idle SLC memory pages.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.