Memory management

US10311241B2 · kind B2 · utility

Assignee

• NXP USA, Inc. · US

Inventors

• Joachim Fader · Munich, DE
• Robert Krutsch · Munich, DE
• Dirk Wendel · Unterhaching, DE

Key dates

• Filing date: Sep 12, 2017
• Grant date: Jun 4, 2019
• Expiry date: Feb 17, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G06F13/1668
• WIPO field: Computer technology
• WIPO sector: Electrical engineering

Abstract

A system on a chip (SoC) and method of operation are described. A data processor has a processor data word size of p×octets and is configured to handle data items having a data item size which is a non-integer multiple of the processor data word size. A memory controller is configured to write or read data items to a memory as multiples of m×octets. Data can be sent between the data processor and the memory controller on a bus. A data protection code generator is configured to generate a data protection code for a data item generated by the data processor before transmitting the data item and the data protection code over the bus to the memory controller which writes at least one octet including at least a portion of the data item and at least a portion of the data protection code to an address. A data protection code checker is configured to receive a read data protection code and a read data item and to check the read data item for an error using the read data protection code. The memory controller reads at least one octet including at least a portion of the read data item and at least a portion of the read data protection code from a read address.