Methods for controlling an end-to-end distance in semiconductor device
US10312089B1 · kind B1 · utility
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20Claims
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Key dates
| Filing date | Mar 16, 2018 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Mar 16, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01J2237/334
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present disclosure may be used for patterning a layer in a 5 nm node or beyond fabrication to achieve an end-to-end distance below 35 nm. Compared to the state of the art technology, embodiments of the present disclosure reduce cycle time and cost of production from three lithographic processes and four etching processes to one lithographic process and three etch processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.