Passivation scheme for pad openings and trenches
US10312207B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 30, 2018 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Jan 30, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/1033
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit (IC) comprising an enhanced passivation scheme for pad openings and trenches is provided. In some embodiments, an interlayer dielectric (ILD) layer covers a substrate and at least partially defines a trench. The trench extends through the ILD layer from a top of the ILD layer to the substrate. A conductive pad overlies the ILD layer. A first passivation layer overlies the ILD layer and the conductive pad, and further defines a pad opening overlying the conductive pad. A second passivation layer overlies the ILD layer, the conductive pad, and the first passivation layer, and further lines sidewalls of the first passivation layer in the pad opening and sidewalls of the ILD layer in the trench. Further, the second passivation layer has a low permeability for moisture or vapor relative to the ILD layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.