Patent · US Active

Asynchronous clock gating circuit

US10312886B2 · kind B2 · utility

0Cited by

3References

9Claims

0Family size

Assignee

INVECAS TECHNOLOGIES PVT. LTD · IN

Inventors

Gyan Prakash · Beaverton, US
Nidhir Kumar · Bengaluru, IN

Key dates

Filing date	Jun 14, 2016
Grant date	Jun 4, 2019
Priority date	—
Expiry date	Jun 14, 2036

Classification

Technology area (CPC H)Electricity
CPC primaryH03K19/0016
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

The present disclosure envisages an asynchronous clock gating circuitry and a method for designing the asynchronous clock gating circuitry. The asynchronous clock gating circuitry could be placed at the very beginning of the clock network, given its design and implementation logic. The asynchronous clock gating circuitry helps meet the timing requirement on the enable pin thereof. The asynchronous clock gating circuitry avoids cumbersome replication of cluck gating circuitry during physical implementation of the (circuit) design, and further helps reduce the power consumption levels in sequential circuits.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.