Gate control for a tristate output buffer
US10312912B2 · kind B2 · utility
0Cited by
5References
6Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2017 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Jun 28, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/0002
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A gate control circuit for a tristate output buffer operating in a first voltage domain includes a pull-up circuit coupled between an upper rail and a first gate control signal, a pull-down circuit coupled between a lower rail and a second gate control signal, and a gate isolation switch coupled between the first gate control signal and the second gate control signal. The gate isolation switch includes a first PMOS transistor coupled in parallel with a first NMOS transistor. The first NMOS transistor is controlled by a first enable signal and the first PMOS transistor is controlled by a second enable signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.