ADC digital gain error compensation
US10312930B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 25, 2018 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Jan 25, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F2203/45594
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Techniques are provided for compensating gain of a combined amplifier and analog-to-digital converter (ADC) circuit, for example, due to additional filtering added to an input of the circuit. In an example, an integrated circuit including an amplifier and ADC can include an amplifier circuit configured to receive an input signal and to amplify the input signal based on an input resistance and a feedback resistance, and to provide an amplified representation of the input signal, and an ADC circuit configured to receive an output of the amplifier, to determine a digital coefficient associated with an additional input resistance coupled to the amplifier, and to provide a compensated digital representation of the amplified representation of the input signal using the digital compensation coefficient.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.