Multi-lane coherent transceiver with synchronized lane reset signals
US10313099B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 4, 2018 |
| Grant date | Jun 4, 2019 |
| Priority date | — |
| Expiry date | Jun 4, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The reset signals output to the lanes of a multi-lane coherent transceiver are synchronized by first synchronizing an asynchronous reset signal to a low-speed clock signal to generate and output a plurality of synchronized reset signals to the lanes. Within each lane, a synchronous reset signal is delayed to generate a number of delayed synchronous reset signals, and the logic states of the synchronous reset signal and the delayed synchronous reset signals are captured. Based on the captured logic states in each of the lanes, a lane synchronized reset signal from the delayed synchronous reset signals is selected for use across all of the lanes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.