System and method for controlling the impact of periodic jitter caused by non-ideal phase interpolators

US10313104B2 · kind B2 · utility

Assignee

• Avago Technologies International Sales Pte. Limited · SG

Inventors

• Amiad Dvir · Irvine, US
• Mike Rolfe Ferrara · Petaluma, US
• Vitaly Zborovski · Herzliya, IL
• Mario Caresosa · Rancho Santa Margarita, US
• Ryan E. Hirth · Windsor, US
• Assaf Naor · Nes Ziona, IL

Key dates

• Filing date: Sep 18, 2017
• Grant date: Jun 4, 2019
• Expiry date: Sep 18, 2037

Classification

• Technology area (CPC H): Electricity
• CPC primary: H04L7/0337
• WIPO field: Digital communication
• WIPO sector: Electrical engineering

Abstract

In some aspects, the disclosure is directed to methods and systems for controlling periodic jitter arising from a phase interpolator (PI). A receiver can receive incoming data. A fractional-N phase-locked loop (PLL) can receive a reference clock. Measurement circuitry can measure a parts per million (PPM) offset between the incoming data and the reference clock, of a PI. The fractional-N PLL can restrict jitter arising from the PI, to frequencies within a predefined bandwidth, by tuning a center frequency of the fractional-N PLL to reduce the PPM offset of the PI.