Two-dimensional array of CMOS control elements
US10315222B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 2016 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | May 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/856
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An electronic device includes a plurality of CMOS control elements arranged in a two-dimensional array, where each CMOS control element of the plurality of CMOS control elements includes two semiconductor devices. The plurality of CMOS control elements include a first subset of CMOS control elements, each CMOS control element of the first subset of CMOS control elements including a semiconductor device of a first class and a semiconductor device of a second class, and a second subset of CMOS control elements, each CMOS control element of the second subset of CMOS control elements including a semiconductor device of the first class and a semiconductor device of a third class. The plurality of CMOS control elements are arranged in the two-dimensional array such that CMOS semiconductor devices of the first class are only adjacent to other CMOS semiconductor devices of the first class, CMOS semiconductor devices of the second class are only adjacent to other CMOS semiconductor devices of the second class, and CMOS semiconductor devices of the third class are only adjacent to other CMOS semiconductor devices of the third class.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.