Substrate structure and method of manufacturing substrate structure
US10317756B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 12, 2018 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Jan 12, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/60
- WIPO fieldOptics
- WIPO sectorInstruments
Abstract
A display substrate includes a base substrate, a gate metal pattern, a semiconductor layer, and a data metal pattern. The base substrate includes a display area and a peripheral area. The gate metal pattern includes a gate electrode of a transistor and includes a gate metal member disposed on the peripheral area. The transistor is disposed on the display area. The semiconductor layer includes a channel portion of the transistor and includes a semiconductor member disposed on the peripheral area. The data metal pattern includes a source electrode of the transistor and includes a data metal member disposed on the peripheral area, electrically connected to the gate metal member, and directly contacting the semiconductor member. A maximum thickness of the data metal member in a direction perpendicular to the base substrate is greater than a maximum thickness of the semiconductor member in the direction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.