Programmable input/output (PIO) engine interface architecture with direct memory access (DMA) for multi-tagging scheme for storage devices
US10318164B2 · kind B2 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 18, 2016 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Jul 16, 2037 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In general, techniques are described by which to provide an interface architecture for storage devices. A storage device comprising non-volatile memory, and a hardware controller may be configured to perform various aspects of the techniques. The hardware controller may be configured to read from or write to one or more data registers in a host device to provide a direct communication channel between each of one or more threads executed by one or more processors of the host device and the hardware controller. The hardware controller may further be configured to send a plurality of commands received from the direct communication channel into a hardware queue, and issue access requests based on the plurality of commands to read data from or write data to the non-volatile memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.