Operation of a multi-slice processor implementing dependency accumulation instruction sequencing
US10318294B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 20, 2016 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Dec 9, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3891
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Operation of a multi-slice processor that includes a plurality of execution slices. Operation of such a multi-slice processor includes: receiving a first instruction indicating a first target register; receiving a second instruction indicating the first target register as a source operand; responsive to the second instruction indicating the first target register as a source operand, updating a dependent count corresponding to the first instruction; and issuing, in dependence upon the dependent count for the first instruction being greater than a dependent count for another instruction, the first instruction to an execution slice of the plurality of execution slices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.