Method and apparatus for operating a self-timed parallelized multi-core processor
US10318297B2 · kind B2 · utility
4Cited by
6References
20Claims
0Family size
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Key dates
| Filing date | Jan 30, 2015 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Mar 5, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A self-timed parallelized multi-core processor has an instruction decoder unit for receiving a program code instruction, determining an operating code and latency for the instruction, and assigning a loop index to the instruction. An instruction decomposer creates a primitive by decomposing the instruction, replacing the loop index with a core index, and broadcasting the primitive. Self-timed processing cores each having a unique core index compare the core index to their unique processing core index. The processing cores act on the primitive when their processing core index is within a threshold of the core index.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.