System and method for an asynchronous processor with pepelined arithmetic and logic unit
US10318305B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 4, 2014 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | May 15, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/4494
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Embodiments are provided for an asynchronous processor with pipelined arithmetic and logic unit. The asynchronous processor includes a non-transitory memory for storing instructions and a plurality of instruction execution units (XUs) arranged in a ring architecture for passing tokens. Each one of the XUs comprises a logic circuit configured to fetch a first instruction from the non-transitory memory, and execute the first instruction. The logic circuit is also configured to fetch a second instruction from the non-transitory memory, and execute the second instruction, regardless whether the one of the XUs holds a token for writing the first instruction. The logic circuit is further configured to write the first instruction to the non-transitory memory after fetching the second instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.