Processing core with operation suppression based on contribution estimate
US10318317B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 10, 2018 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | May 10, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/4824
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Processing cores with the ability to suppress operations based on a contribution estimate for those operation for purposes of increasing the overall performance of the core are disclosed. Associated methods that can be conducted by such processing cores are also disclosed. One such method includes generating a reference value for a composite computation. A complete execution of the composite computation generates a precise output and requires execution of a set of component computations. The method also includes generating a component computation approximation. The method also includes evaluating the component computation approximation with the reference value. The method also includes executing a partial execution of the composite computation using the component computation approximation to produce an estimated output. The method also includes suppressing the component computation, while executing the partial execution, based on the evaluation of the component computation approximation with the reference value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.