Secure memory access using memory read restriction
US10318438B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Dec 7, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2029/0401
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus includes a memory, an interface and read restriction logic. The read restriction logic is configured to receive via the interface a request to read a data value from a specified address of the memory, to retrieve the data value from the specified address, to check, upon finding that the specified address falls in an address range that is predefined as restricted, whether the retrieved data value belongs to a predefined set of permitted data values, to respond to the request with the retrieved data value when the retrieved data value belongs to the set of permitted data values, and, otherwise, when the retrieved data value does not belong to the set of permitted data values, to respond to the request with a dummy data value.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.