Collective memory transfer devices and methods for multiple-core processors
US10318444B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 10, 2014 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Dec 7, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This disclosure provides systems, methods, and apparatus for collective memory transfers. A control unit may be configured to coordinate a transfer of data between a memory and processor cores. For a read data transfer operation, the control unit may receive a trigger packet identifying a read data transfer operation and identifying a first plurality of data lines based on data values included in the trigger packet. The control unit may read the first plurality of data lines from the memory sequentially and send a second plurality of data lines to the processor cores. For a write data transfer operation, the control unit may send a request for at least one data line to a plurality of processor cores, may receive and reorder the requested data lines, and may write the data lines to a memory. The control unit may determine a mapping between processor cores and the memory.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.