Method and apparatus for split burst bandwidth arbitration
US10318457B2 · kind B2 · utility
0Cited by
4References
21Claims
0Family size
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Key dates
| Filing date | May 31, 2016 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Sep 29, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/37
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An embedded system and method for controlling such are disclosed. The embedded system includes a direct memory controller comprising a plurality of channels, wherein a plurality of channel arbitration schemes are programmable, wherein the DMA controller is programmable to split a block data transfer on a specified channel into a plurality of separate data transfers, wherein a data transfer on a specified channel can be interrupted between separate data transfers of the data transfer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.