Semiconductor memory device, memory system, and method using bus-invert encoding
US10318469B2 · kind B2 · utility
2Cited by
6References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2015 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Dec 29, 2035 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D10/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device comprises a memory cell array and a data inversion circuit. The data inversion circuit is configured to receive a first unit data and a second unit data stored in the memory cell array through different first data lines, determine, while the first unit data is transmitted to a data input/output (I/O) buffer through a second data line, whether to the invert the second unit data based on a Hamming distance between the first unit data and the second unit data, and transmit the inverted or non-inverted second unit data to the data I/O buffer through the second data line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.