Patent · US Active

Build synthesized soft arrays

US10318688B2 · kind B2 · utility

0Cited by
3References
20Claims
0Family size

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Inventors

Key dates

Filing dateMar 27, 2017
Grant dateJun 11, 2019
Priority date
Expiry dateMar 29, 2037

Classification

  • Technology area (CPC Y)Emerging Cross-Sectional Technologies
  • CPC primaryY02P90/02
  • WIPO fieldComputer technology
  • WIPO sectorElectrical engineering

Abstract

Generating design data for manufacturing a logic array of a semiconductor circuit from specification data describing the logic array. The specification is transformed into structured specification data including objects corresponding to circuit cells of a first type and logic specification data specifying the logic circuitry to be included in the logic array, and into structure data including placing and routing information concerning the circuit cells of the first type. A determination is made of circuit cells of a second type from the logic specification data. The circuit cells of the first type are pre-placed and routed based on the structure data. The circuit cells of second type are automatically placed and routed.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.