Modifying a manufacturing process of integrated circuits based on large scale quality performance prediction and optimization
US10318700B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 5, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Nov 12, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L22/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method modifies a manufacturing process for integrated circuits. One or more processors receive sensor readings that identify failed integrated circuits from a batch of integrated circuits, where each of the integrated circuits includes a set of dynamic random access memory (DRAM) chips and a memory buffer, where the memory buffer provides an interface between a memory controller and the DRAM chips. The processor(s) identify, based on the sensor readings, a performance trending estimate of DRAM failures versus memory buffer failures in the identified failed integrated circuits. The processor(s) predict a fault analysis (FA) pareto based on the performance trending estimate, a location and address of each DRAM in the identified failed integrated circuits, and a wafer location on the wafer die on which each memory buffer that has the memory buffer failure, such that a manufacturing process for the integrated circuits is modified based on the FA pareto.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.