Gate driving circuit and display device including the same
US10319283B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 7, 2016 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Jul 13, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2310/0291
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
Provided are a gate driving circuit and a display device including the same. The gate driving circuit according to an embodiment includes a shift register including a plurality of stages. An nth stage of the stages includes a latch control circuit including a first NMOS transistor connected to a QB node, a second NMOS transistor connected to a Q node, and a third NMOS transistor having a gate electrode to which a first clock is input and connected to the first and second NMOS transistors, where n is a positive integer. A latch is connected between the Q and QB nodes. A transmission gate is connected to the Q and QB nodes. In the gate driving circuit, output signals of a previous stage and a following stage are controlled so as to be synchronized with the first clock to suppress a glitch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.