Memory device with a low-current reference circuit
US10319423B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Nov 1, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C2207/063
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device includes a memory cell unit, a reference circuit, and a sense amplifier. The memory cell unit includes a memory cell. The reference circuit is configured to generate a reference current and includes a plurality of magnetic resistive elements. At least one of the magnetic resistive elements is in a high resistance state. The sense amplifier is coupled to the memory cell unit and the reference circuit and is configured to compare a current that flows through the memory cell to the reference current to sense a bit of data stored in the memory cell, to amplify a level of the sensed bit of data, and to output the amplified bit of data.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.