Fluid ejection devices comprising memory cells
US10319728B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 14, 2016 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Mar 3, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldTextile and paper machines
- WIPO sectorMechanical engineering
Abstract
In some examples, a fluid ejection device includes a substrate and a memory cell on the substrate, the memory cell including a first dielectric layer, a floating gate, a second dielectric layer, and a control gate. The memory cell includes a channel region between a drain region and a source region. The first dielectric layer is over the channel region and the floating gate is capacitively coupled to the channel region through the first dielectric layer. The floating gate includes a polysilicon layer, a metal layer, and a second dielectric layer between the polysilicon layer and the metal layer, where the second dielectric layer includes an opening through which the polysilicon layer is electrically connected to the metal layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.