Three dimensional semiconductor memory devices
US10319738B2 · kind B2 · utility
8Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 15, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Dec 15, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C8/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A three-dimensional semiconductor memory device includes a cell string vertically extending from a top surface of a substrate and having first and second cell transistors, first and second word lines connected to gate electrodes of the first and second cell transistors respectively, a first pass transistor connecting the first word line to a row decoder, and a second pass transistor connecting the second word line to the row decoder. The first pass transistor includes a plurality of first sub-transistors connected in parallel between the first word line and the row decoder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.