Patent · US Active

Array substrate, display panel, and display apparatus

US10319747B2 · kind B2 · utility

0Cited by
1References
19Claims
0Family size

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Key dates

Filing dateJul 1, 2016
Grant dateJun 11, 2019
Priority date
Expiry dateJul 1, 2036

Classification

  • Technology area (CPC G)Physics
  • CPC primaryG02F2201/123
  • WIPO fieldOptics
  • WIPO sectorInstruments

Abstract

An array substrate includes: a plurality of pixels including sub-pixels forming a matrix, each sub-pixel including a pair of sub-pixel portions; a plurality of data lines; a plurality of gate lines intersecting with the plurality of data lines; and a plurality of pairs of transistors configured to control the plurality of pairs of sub-pixel portions; wherein: each pair of transistors are disposed adjacent to an intersection between a gate line and a data line, across at least one of the gate line or the data line, and are configured to control a pair of sub-pixel portions in neighboring rows or columns of sub-pixel portions.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.