Reduced VSWR switching
US10320381B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 27, 2015 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Nov 1, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K17/165
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Sequenced switching mitigates impedance variations and signal reflections during switching events by stepping a switch incrementally through a sequence of different states from a start state to at least one intermediate state to an end state. Various architectures, sequencing and step control techniques may permit any degree of mitigation, including to the point of essentially eliminating impedance glitches. Sequential reconfiguration of the structure and/or parameters of one or more switch branches may permit simplification of related programming and circuitry while increasing the lifespan of components spared from unmitigated current and voltage spikes. Each switch branch being transitioned during a switch event may sequence differently than other branches based on the start state, end state and configuration of each branch.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.