Field programmable gate array including coupled lookup tables
US10320390B1 · kind B1 · utility
13Cited by
7References
15Claims
0Family size
Inventor
Key dates
| Filing date | Nov 13, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Dec 1, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/1776
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A reconfigurable field programmable gate array (FPGA) includes: a first logic block having a first lookup table; and a second logic block having a second lookup table, wherein the first logic block is coupled to the second logic block, in which the first logic block is configured to pass, upon a clock cycle of the FPGA, data about a lookup table configuration stored in the first lookup table to the second logic block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.