Scaleable DLL clocking system
US10320399B2 · kind B2 · utility
0Cited by
13References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 8, 2018 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Jun 8, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/135
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A clocking system disclosed herein includes a delay locked loop (DLL) circuit with a plurality of delay elements, where the DLL circuit is configured to receive a clock input signal and generate a plurality of clock output signals. The clocking system also includes a feed-forward system configured to increase the speed of the clock signal transmission through the delay elements and to enforce symmetric zero crossings of the clock signal at each of the plurality of delay elements.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.