Phase-locked loop with high bandwidth using rising edge and falling edge of signal
US10320400B2 · kind B2 · utility
1Cited by
3References
17Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Oct 13, 2016 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Oct 13, 2036 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/099
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
Disclosed is a phase-locked loop having a high bandwidth using the rising edge and falling edge of a signal. The disclosed phase-locked loop controls the frequency of a voltage control oscillator by comparing both a phase difference between rising edge of a reference signal and rising edge of a feedback signal and a phase difference between falling edge of the reference signal and falling edge of the feedback signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.