Sampling clock generating circuit and analog to digital converter
US10320409B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 8, 2017 |
| Grant date | Jun 11, 2019 |
| Priority date | — |
| Expiry date | Sep 8, 2037 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03M1/1215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A sampling clock generating circuit and an analog to digital converter includes a variable resistance circuit, and a NOT-gate type circuit, where an input end of the NOT-gate type circuit receives a pulse signal whose period is T; a power supply terminal of the NOT-gate type circuit is connected to a power supply; a ground terminal of the NOT-gate type circuit is connected to one end of the variable resistance circuit; and the other end of the variable resistance circuit is grounded; the NOT-gate type circuit is configured to: when the pulse signal is a high level, output a low level; and when the pulse signal is a low level, output a high level.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.