Laser-based integrated circuit testing techniques

US10324131B1 · kind B1 · utility

Assignee

• QUALCOMM Incorporated · US

Inventors

• Lesly Zaren Venturina Endrinal · San Diego, US
• Rakesh Kumar Kinger · San Diego, US
• Joseph Y. Fang · Katy, US
• Srinivas Patil · Austin, US
• Lavakumar Ranganathan · San Diego, US
• Chia-Ying Chen · Taipei, TW

Key dates

• Filing date: Jan 16, 2018
• Grant date: Jun 18, 2019
• Expiry date: Jan 16, 2038

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/318558
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

The present disclosure provide techniques for semiconductor testing, and more particularly, to systems and methods for laser-based fault isolation and design for testability (DFT) diagnosis techniques. In one embodiment, an integrated chip (IC) testing apparatus, includes an input pin; a decompressor connected to the input pin; a plurality of scan chains, each scan chain of the plurality of scan chains comprising a plurality of scan cells; a plurality of scan chain control elements, each scan chain control element of the plurality of scan chain control elements being connected between the decompressor and a respective scan chain of the plurality of scan chains, wherein each scan chain control element is configured to enable or disable test data from flowing from the compressor to the respective scan chain; a compressor connected to an output of each scan chain of the plurality of scan chains; and an output pin connected to the compressor.