Controlling forced idle state operation in a processor
US10324519B2 · kind B2 · utility
6Cited by
23References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jun 23, 2016 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Oct 13, 2036 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY02D30/50
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In one embodiment, a processor includes a plurality of cores and a power controller including a first logic, responsive to a determination that the processor resided in a forced idle state for less than a threshold duration, to update a first counter and, responsive to a value of the first counter that exceeds a control threshold, prevent the processor from entry into the forced idle state. Other embodiments are described and claimed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.