Hardware apparatuses and methods to fuse instructions
US10324724B2 · kind B2 · utility
5Cited by
2References
24Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 16, 2015 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Apr 28, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30196
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methods and apparatuses relating to a fusion manager to fuse instructions are described. In one embodiment, a hardware processor includes a hardware binary translator to translate an instruction stream into a translated instruction stream, a hardware fusion manager to fuse multiple instructions of the translated instruction stream into a single fused instruction, a hardware decode unit to decode the single fused instruction into a decoded, single fused instruction, and a hardware execution unit to execute the decoded, single fused instruction.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.