Error checking of a multi-threaded computer processor design under test
US10324815B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 14, 2017 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Jun 24, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2115/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Error checking for a computer processor design under test. In multiple processing threads, and in accordance with a hardware model of a computer processor design under test, the instructions of multiple instruction sequences corresponding to the processing threads are processed, thereby resulting in an order in which the instructions are processed in accordance with the hardware model, and producing an actual result for each of the instructions. An expected result is determined for any of the instructions in accordance with a reference model of the computer processor design under test and in accordance with the order in which the instructions were processed in accordance with the hardware model. Any of the instructions whose expected result and actual result differ are identified.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.