Distributed hardware tracing
US10324817B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 19, 2018 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Jan 19, 2038 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2201/865
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A computer-implemented method executed by one or more processors, the method includes monitoring execution of program code executed by a first processor component; and monitoring execution of program code executed by a second processor component. A computing system stores data identifying hardware events in a memory buffer. The stored events occur across processor units that include at least the first and second processor components. The hardware events each include an event time stamp and metadata characterizing the event. The system generates a data structure identifying the hardware events. The data structure arranges the events in a time ordered sequence and associates events with at least the first or second processor components. The system stores the data structure in a memory bank of a host device and uses the data structure to analyze performance of the program code executed by the first or second processor components.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.