Information processing apparatus and data transfer method
US10324866B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 23, 2016 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Jan 23, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K15/1817
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An information processing apparatus includes a first, second, and third chips connected in series. The second chip includes a receiving unit, a register, a determination unit, an address translation unit, a controller unit, and a transmission unit. The receiving unit receives data and address information from the first chip. The determination unit determines whether the received address information corresponds to an address translation area based on address translation information set to the register. The address translation unit outputs translated address information to an internal bus. The controller unit controls to store data to which address information corresponding to an address area set for the second chip is attached. The transmission unit transmits to the third chip data to which address information is attached. The address translation unit translates address information corresponding to an address area set for the second chip into an address destination in the second chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.