Counter with reduced memory access
US10324868B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Aug 24, 2015 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Aug 24, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L43/20
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention relates to a counting unit (100) configured to count an amount of traffic events of a data packet traffic. The counting unit comprises a counting element (131) configured to store a value representing the amount of traffic events. The counting unit further comprises a processing unit (120-123) configured to detect an arrival of each data packet of the data packet traffic at the processing unit, to process each data packet and to determine whether the value at counting element (131) should be increased each time the arrival of one data packet is detected at the processing unit, wherein the processing unit (120-123) is configured to store a probability value pc<1 indicating a probability that the processing unit increases the value at the counting element each time the arrival of one data packet is detected at the processing unit, wherein the processing unit is configured such that when it detects the arrival of one data packet at the processing unit, it increases the value at the counting element only with the probability pc.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.