Memory circuit with integrated processor
US10324870B2 · kind B2 · utility
0Cited by
6References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 12, 2016 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Feb 12, 2036 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/1636
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory circuit having: a memory array including one or more memory banks; a first processor; and a processor control interface for receiving data processing commands directed to the first processor from a central processor, the processor control interface being adapted to indicate to the central processor when the first processor has finished accessing one or more of the memory banks of the memory array, these memory banks becoming accessible to the central processor.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.