Patent · US Active

Interrupt-vector translation lookaside buffer

US10324872B2 · kind B2 · utility

0Cited by

3References

17Claims

0Family size

Assignee

Intel IP Corporation · US

Inventors

Xiang Zou · Beaverton, US
Hong Wang · Beijing, CN
Gautham Chinya · Hillsboro, US
Perry Wang · San Jose, US

Key dates

Filing date	Sep 20, 2016
Grant date	Jun 18, 2019
Priority date	—
Expiry date	Mar 11, 2037

Classification

Technology area (CPC G)Physics
CPC primaryG06F2212/68
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

Systems, Methods and apparatuses relating to processor cores that respond to interrupts are disclosed. In one embodiment, an apparatus includes an interrupt interface, a memory interface; and a processor core to generate an interrupt acknowledge signal in response to a received interrupt; receive data in return; determine whether the received data is an interrupt service routine address, the interrupt service routine address being stored in an interrupt vector translation lookaside buffer; and, if not, use the received data to calculate the interrupt service routine address; wherein the processor core is further to use the interrupt service routine address to issue a request on the memory interface to fetch the interrupt service routine, and to execute the interrupt service routine.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.