Virtual directory navigation and debugging across multiple test configurations in the same session

US10325048B1 · kind B1 · utility

Assignee

• Cadence Design Systems, Inc. · US

Inventors

• Sameer Chakravarthy Chillarige · Bengaluru, IN
• Sonam Kathpalia · Sidhauli, IN
• Mehakpreet Kaur · Amritsar, IN
• James Allen · Capistrano Beach, US
• Krishna Vijaya Chakravadhanula · Vestal, US

Key dates

• Filing date: Dec 14, 2016
• Grant date: Jun 18, 2019
• Expiry date: Dec 14, 2036

Classification

• Technology area (CPC G): Physics
• CPC primary: G01R31/31912
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An integrated circuit test method provides an interactive shell environment having analysis modules organized as a directory such that for a given session a user can access any of the analysis modules. This invention describes a virtual directory structure for navigating through the entire test data starting from design, test configuration, ATPG patterns, failure information and callout information. This structure also allows the creation of a scripting environment for the user to select a specific configuration and process the information. User can achieve all of this in a single session as opposed to working on every test configuration in an independent session.