Signal integrity delay utilizing a window bump-based aggressor alignment scheme
US10325055B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 3, 2015 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Jul 4, 2035 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2119/12
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
This application discloses a computing system configured to determine a timing window for reception of a signal propagated through a victim channel in a circuit design, generate an aggressor window bump for each noise bump capable of being induced on the victim channel by one or more aggressor channels, determine a delta delay corresponding to the timing window for the signal propagated through the victim channel based, at least in part, on one or more of the aggressor window bump, and utilize the delta delay corresponding to the timing window for the signal to determine whether the victim channel operates within a timing constraint associated with the circuit design.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.