Circuit for testing display panel, method for testing display panel, and display panel
US10325535B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Jan 31, 2017 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Aug 20, 2037 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG09G2330/12
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A method for testing a display panel includes: applying a first level signal to a first sub-pixel and a third sub-pixel of a first pixel unit and applying a second level signal to a second sub-pixel of the first pixel unit; applying the second level signal to a first sub-pixel and a third sub-pixel of a second pixel unit and applying the first level signal to a second sub-pixel of the second pixel unit; and detecting a short circuit between adjacent sub-pixels. The first level signal has a voltage polarity opposite to a voltage polarity of the second level signal. Therefore, it is ensured that any two adjacent sub-pixels have opposite voltage polarities when the short circuit between adjacent sub-pixels of the display panel is detected. The method also provides improved testing abilities to detect an open circuit in a sub-pixel.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.