Patent · US Active

Ternary sense amplifier and SRAM array realized by the ternary sense amplifier

US10325649B2 · kind B2 · utility

1Cited by

3References

4Claims

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Assignee

Ningbo University · CN

Inventors

Pengjun Wang · Zhejiang, CN
Daohui Gong · Ningbo City, CN
Yaopeng Kang · Zhejiang, CN
Huihong Zhang · Zhejiang, CN

Key dates

Filing date	Aug 24, 2017
Grant date	Jun 18, 2019
Priority date	—
Expiry date	Nov 28, 2037

Classification

Technology area (CPC H)Electricity
CPC primaryH10K19/10
WIPO fieldComputer technology
WIPO sectorElectrical engineering

Abstract

A ternary sense amplifier and an SRAM array realized by the ternary sense amplifier are provided. The ternary sense amplifier comprises the 1st CNFET transistor, the 2nd CNFET transistor, the 3rd CNFET transistor, the 4th CNFET transistor, the 5th CNFET transistor, the 6th CNFET transistor, the 7th CNFET transistor, the 8th CNFET transistor, the 9th CNFET transistor, the 10th CNFET transistor, the 11th CNFET transistor, the 12th CNFET transistor and the 13th CNFET transistor; the SRAM array comprises a ternary sense amplifier, a ternary memory array, the 1st inverter, the 2nd inverter, the 3rd inverter, the 4th inverter, the 14th CNFET transistor, the 15th CNFET transistor, the 16th CNFET transistor, the 17th CNFET transistor, the 18th CNFET transistor and the 19th CNFET transistor; it features in low power consumption, less postponement and high yield of chips.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.