Integrated circuit with connectivity error detection
US10325836B1 · kind B1 · utility
2Cited by
3References
18Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2018 |
| Grant date | Jun 18, 2019 |
| Priority date | — |
| Expiry date | Jul 13, 2038 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/00014
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An integrated circuit with transmission line error detection comprises a substrate, a package enclosing the substrate, a lead extending from the inside of the package to the outside of the package, and a circuit supported by the substrate. The circuit includes an input circuit and an output circuit. A first wire is coupled between the output circuit and the lead and a second wire is coupled between the lead and the input circuit so that the input circuit receives a signal generated by the output circuit after the signal has been transmitted across the first and second wires.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.