Patent · US Active

Edge interconnect packaging of integrated circuits for power systems

US10325875B2 · kind B2 · utility

0Cited by

2References

20Claims

0Family size

Assignees

North Carolina State University · US
Indiana Integrated Circuits, LLC · US

Inventors

Jason M. Kulick · South Bend, US
Douglas Hopkins · Raleigh, US

Key dates

Filing date	Jul 17, 2015
Grant date	Jun 18, 2019
Priority date	—
Expiry date	Aug 20, 2035

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/13091
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Disclosed is an integrated circuit packaging system that includes first and second microchips. Each microchip includes a top surface, a surface, one or more quilt package nodules fabricated on said top surface, and one or more bottom surface connectors. The system also includes a substrate to which the first and second microchips are mounted. The first and second microchips are connected via the quilt package nodules.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.